1. Technical Field of the Invention
The present invention relates to circuits and more particularly, to a dynamic threshold source follower voltage driver circuit.
2. Background Art
A driver circuit is used to provide the ability to quickly change the input voltage of a receiver circuit that it drives. Instances in which a driving circuit may be used include to drive a relatively long interconnect conductor and to drive a wide fan-out set of conductors. A commonly used driver circuit includes first and second inverters connected in series, wherein each inverter includes a pull-up p-channel metal oxide semiconductor field effect transistor (pMOSFET) in series with a pull down n-channel MOSFET (nMOSFET). The input to the driver is the input to the first inverter. The output of the first inverter is the input to the second inverter and the output of the second inverter is the output of the driver.
Point-to-point on-chip interconnects between and within microprocessor datapath Functional Unit Blocks (FUBs) have evolved with integration as major on-chip performance and power bottlenecks. A reason for this is that interconnect capacitance per unit length, dominated by sidewall fringing and cross-coupling, may increase hyperbolically with lateral dimension scaling and hence scale slower than gate capacitance does, despite technology enhancements such as low-K dielectric materials and copper metallization.
Dynamic threshold (Vt) based circuit techniques have been investigated for low-voltage datapath circuits and interconnect drivers. See, e.g., F. Assaderaghi et al., "A Dynamic Threshold Voltage MOS (DTMOS) for Very Low Voltage Operation," IEEE Electron Device Letters, December 1994, pp. 510-512; and U.S. Pat. No. 5,559,368. These circuits possess "dynamic" Vt transistors, i.e., transistors whose Vt changes as the gate switches. Therefore, as the input transitions, the gate-to-bulk forward bias voltage of the switching transistor increases, causing a Vt reduction (due to body effect) as the gate switches. However, since the bulk terminals are directly tied to the inputs, the fan-in gate capacitance is now substantially higher. This significantly degrades the potential performance benefits and may contribute to higher switched capacitance, and hence higher switching power consumption. Further, since each transistor must have its gate and bulk connected, a separate well is required for each device, resulting in considerable layout area penalties.